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NXP Semiconductors /MKW41Z4 /NVIC /NVIC_ISPR

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Interpret as NVIC_ISPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SETPEND0 0 (0)SETPEND1 0 (0)SETPEND2 0 (0)SETPEND3 0 (0)SETPEND4 0 (0)SETPEND5 0 (0)SETPEND6 0 (0)SETPEND7 0 (0)SETPEND8 0 (0)SETPEND9 0 (0)SETPEND10 0 (0)SETPEND11 0 (0)SETPEND12 0 (0)SETPEND13 0 (0)SETPEND14 0 (0)SETPEND15 0 (0)SETPEND16 0 (0)SETPEND17 0 (0)SETPEND18 0 (0)SETPEND19 0 (0)SETPEND20 0 (0)SETPEND21 0 (0)SETPEND22 0 (0)SETPEND23 0 (0)SETPEND24 0 (0)SETPEND25 0 (0)SETPEND26 0 (0)SETPEND27 0 (0)SETPEND28 0 (0)SETPEND29 0 (0)SETPEND30 0 (0)SETPEND31

SETPEND2=0, SETPEND22=0, SETPEND11=0, SETPEND23=0, SETPEND18=0, SETPEND24=0, SETPEND16=0, SETPEND14=0, SETPEND31=0, SETPEND19=0, SETPEND7=0, SETPEND26=0, SETPEND9=0, SETPEND28=0, SETPEND5=0, SETPEND1=0, SETPEND13=0, SETPEND20=0, SETPEND3=0, SETPEND15=0, SETPEND12=0, SETPEND27=0, SETPEND30=0, SETPEND25=0, SETPEND10=0, SETPEND29=0, SETPEND17=0, SETPEND21=0, SETPEND6=0, SETPEND0=0, SETPEND8=0, SETPEND4=0

Description

Interrupt Set Pending Register

Fields

SETPEND0

DMA channel 0 transfer complete/error interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 0 transfer complete/error interrupt is not pending

1 (1): write: changes the DMA channel 0 transfer complete/error interrupt state to pending; read: DMA channel 0 transfer complete/error interrupt is pending
SETPEND1

DMA channel 1 transfer complete/error interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 1 transfer complete/error interrupt is not pending

1 (1): write: changes the DMA channel 1 transfer complete/error interrupt state to pending; read: DMA channel 1 transfer complete/error interrupt is pending
SETPEND2

DMA channel 2 transfer complete/error interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 2 transfer complete/error interrupt is not pending

1 (1): write: changes the DMA channel 2 transfer complete/error interrupt state to pending; read: DMA channel 2 transfer complete/error interrupt is pending
SETPEND3

DMA channel 3 transfer complete/error interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 3 transfer complete/error interrupt is not pending

1 (1): write: changes the DMA channel 3 transfer complete/error interrupt state to pending; read: DMA channel 3 transfer complete/error interrupt is pending
SETPEND4

Reserved iv 20 interrupt set-pending bit

0 (0): write: no effect; read: Reserved iv 20 interrupt is not pending

1 (1): write: changes the Reserved iv 20 interrupt state to pending; read: Reserved iv 20 interrupt is pending
SETPEND5

Flash command complete and read collision interrupt set-pending bit

0 (0): write: no effect; read: Flash command complete and read collision interrupt is not pending

1 (1): write: changes the Flash command complete and read collision interrupt state to pending; read: Flash command complete and read collision interrupt is pending
SETPEND6

Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt set-pending bit

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt is not pending

1 (1): write: changes the Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt state to pending; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt is pending
SETPEND7

Low Leakage Wakeup interrupt set-pending bit

0 (0): write: no effect; read: Low Leakage Wakeup interrupt is not pending

1 (1): write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending
SETPEND8

Inter-Integrated Circuit 0 interrupt set-pending bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending

1 (1): write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending
SETPEND9

Inter-Integrated Circuit 1 interrupt set-pending bit

0 (0): write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending

1 (1): write: changes the Inter-Integrated Circuit 1 interrupt state to pending; read: Inter-Integrated Circuit 1 interrupt is pending
SETPEND10

Serial Peripheral Interface 0 interrupt set-pending bit

0 (0): write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending

1 (1): write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending
SETPEND11

Touch Sensing Input interrupt set-pending bit

0 (0): write: no effect; read: Touch Sensing Input interrupt is not pending

1 (1): write: changes the Touch Sensing Input interrupt state to pending; read: Touch Sensing Input interrupt is pending
SETPEND12

LPUART0 status and error interrupt set-pending bit

0 (0): write: no effect; read: LPUART0 status and error interrupt is not pending

1 (1): write: changes the LPUART0 status and error interrupt state to pending; read: LPUART0 status and error interrupt is pending
SETPEND13

True Random Number Generator interrupt set-pending bit

0 (0): write: no effect; read: True Random Number Generator interrupt is not pending

1 (1): write: changes the True Random Number Generator interrupt state to pending; read: True Random Number Generator interrupt is pending
SETPEND14

Carrier modulator transmitter interrupt set-pending bit

0 (0): write: no effect; read: Carrier modulator transmitter interrupt is not pending

1 (1): write: changes the Carrier modulator transmitter interrupt state to pending; read: Carrier modulator transmitter interrupt is pending
SETPEND15

Analog-to-Digital Converter 0 interrupt set-pending bit

0 (0): write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending

1 (1): write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending
SETPEND16

DMA channel 0 - 31 error interrupt set-pending bit

0 (0): write: no effect; read: DMA channel 0 - 31 error interrupt is not pending

1 (1): write: changes the DMA channel 0 - 31 error interrupt state to pending; read: DMA channel 0 - 31 error interrupt is pending
SETPEND17

Timer/PWM module 0 interrupt set-pending bit

0 (0): write: no effect; read: Timer/PWM module 0 interrupt is not pending

1 (1): write: changes the Timer/PWM module 0 interrupt state to pending; read: Timer/PWM module 0 interrupt is pending
SETPEND18

Timer/PWM module 1 interrupt set-pending bit

0 (0): write: no effect; read: Timer/PWM module 1 interrupt is not pending

1 (1): write: changes the Timer/PWM module 1 interrupt state to pending; read: Timer/PWM module 1 interrupt is pending
SETPEND19

Timer/PWM module 2 interrupt set-pending bit

0 (0): write: no effect; read: Timer/PWM module 2 interrupt is not pending

1 (1): write: changes the Timer/PWM module 2 interrupt state to pending; read: Timer/PWM module 2 interrupt is pending
SETPEND20

Real-time counter interrupt set-pending bit

0 (0): write: no effect; read: Real-time counter interrupt is not pending

1 (1): write: changes the Real-time counter interrupt state to pending; read: Real-time counter interrupt is pending
SETPEND21

RTC seconds interrupt set-pending bit

0 (0): write: no effect; read: RTC seconds interrupt is not pending

1 (1): write: changes the RTC seconds interrupt state to pending; read: RTC seconds interrupt is pending
SETPEND22

Periodic Interrupt Timer interrupt set-pending bit

0 (0): write: no effect; read: Periodic Interrupt Timer interrupt is not pending

1 (1): write: changes the Periodic Interrupt Timer interrupt state to pending; read: Periodic Interrupt Timer interrupt is pending
SETPEND23

LTC0 interrupt set-pending bit

0 (0): write: no effect; read: LTC0 interrupt is not pending

1 (1): write: changes the LTC0 interrupt state to pending; read: LTC0 interrupt is pending
SETPEND24

Radio 0 interrupt set-pending bit

0 (0): write: no effect; read: Radio 0 interrupt is not pending

1 (1): write: changes the Radio 0 interrupt state to pending; read: Radio 0 interrupt is pending
SETPEND25

Digital to Analog Converter interrupt set-pending bit

0 (0): write: no effect; read: Digital to Analog Converter interrupt is not pending

1 (1): write: changes the Digital to Analog Converter interrupt state to pending; read: Digital to Analog Converter interrupt is pending
SETPEND26

Radio 1 interrupt set-pending bit

0 (0): write: no effect; read: Radio 1 interrupt is not pending

1 (1): write: changes the Radio 1 interrupt state to pending; read: Radio 1 interrupt is pending
SETPEND27

Multipurpose Clock Generator interrupt set-pending bit

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt is not pending

1 (1): write: changes the Multipurpose Clock Generator interrupt state to pending; read: Multipurpose Clock Generator interrupt is pending
SETPEND28

Low-Power Timer 0 interrupt set-pending bit

0 (0): write: no effect; read: Low-Power Timer 0 interrupt is not pending

1 (1): write: changes the Low-Power Timer 0 interrupt state to pending; read: Low-Power Timer 0 interrupt is pending
SETPEND29

Serial Peripheral Interface 1 interrupt set-pending bit

0 (0): write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending

1 (1): write: changes the Serial Peripheral Interface 1 interrupt state to pending; read: Serial Peripheral Interface 1 interrupt is pending
SETPEND30

Pin detect Port A interrupt set-pending bit

0 (0): write: no effect; read: Pin detect Port A interrupt is not pending

1 (1): write: changes the Pin detect Port A interrupt state to pending; read: Pin detect Port A interrupt is pending
SETPEND31

Pin detect Port B and C interrupt set-pending bit

0 (0): write: no effect; read: Pin detect Port B and C interrupt is not pending

1 (1): write: changes the Pin detect Port B and C interrupt state to pending; read: Pin detect Port B and C interrupt is pending

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of the copyright holder nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data